遠藤和彦
略歴
平成3．３ 早稲田大学理工学部電子通信学科卒業
平成３．４ 早稲田大学理工学研究科修士課程電気工学専攻入学平成
５．３ 早稲田大学理工学研究科修士課程電気工学専攻修了 平成５．４ 日本電気株式会社 マイクロエレクトロニクス研究所 入社
平成１６．４ 産業技術総合研究所 エレクトロニクス研究部門 入所
平成１９．４ 産業技術総合研究所 エレクトロニクス研究部門 主任研究員
平成２７．４ 産業技術総合研究所 ナノエレクトロニクス研究部門 研究グループ長平成２９．４ 東北大学流体科学研究所教授（クロスアポイントメント）(～令和３．３)
令和４．４ 産業技術総合研究所 デバイス技術研究部門 総括研究主幹
令和４．１１ 東北大学 流体科学研究所 教授
学会活動
2006年 International Conference on Solid State Device and Materials (SSDM)
SteeringCommittee 2006 - 2016
2008年 応用物理学会シリコンテクノロジー分科会幹事 2008 - 2018
2009年 Silicon Nanoelectronics Workshop (SNW) Program Committee 2009-2022
2012年 International Electron Device Meeting (IEDM) Program Committee 2012
- 20132014 年 IEEE International Nanoelectronics Conference 2014 Organizing
Committee
2014 年 応用物理学会代議員 2014 - 2017
2015 年 電気学会調査専門委員会 ナノエレクトロニクス新機能創出・集積化技術調査専門委員会 委員 2015 - 20202016年 IEEE
International Conference on Nanotechnology (IEEE Nano) 2016 Organizing
Committee
2016年 VLSI Symposium on Technology Program Committee 2016 - 20222019年 応用物理学会シリコンテクノロジー分科会 副幹事長
2019 - 20202020年 Advanced Metallization Conference Program Committee 2020
- 2022
2021年 応用物理学会シリコンテクノロジー分科会 幹事長 2021- 2022
2021年 応用物理学会論文賞選考委員 2021 - 20222021年 電気学会調査専門委員会 ナノエレクトロニクス機能化・応用技術調査専門委員会 委員長
2021-2022
2021年 応用物理学会システムデバイスロードマップ産学連携委員会 運営委員会委員2021-2022
受賞 1999.3 応用物理学会 第5回応用物理学会講演奨励賞
1999.5 日本電気株式会社 研究開発グループ 「功績賞および石黒賞」（内部表彰）
2003.10 Advanced Metallization Conference, “ADMETA Award 2003” A Highly
Reliable Barrier Dielectric for Cu/SiOC Interconnects from Trimethylvinylsilane K.
Endo, N. Morita, T. Usami, K. Ohto and H. Miyamoto
2016.10 IEEE International Conference on Nanotechnology, “Best Paper Award”
Defect-Free Germanium Etching for 3D Fin MOSFET Using Neutral Beam Etching
En-Tzu Lee, Shuichi Noda, Wataru Mizubayashi, Kazuhiko Endo, Seiji Samukawa
招待講演
1. Plasma deposition of low-dielectric-constant fluorinated amorphous carbon
interlayer dielectrics 45th International American Vauum Society Symposium,
PS-ThM5, Baltimore, 1998. K. Endo
2. Low-k fluorinated amorphous carbon for ULSI multilevel interconnection
Dielectrics for ULSI Multilevel Interconnection Conference, Santa Clara,
1999. K. Endo, Y. Matsubara, K. Kishimoto, M. Iguchi, T. Matsui, K. Shinoda,
T. Horiuchi and H. Gomi
3. Current Status and Future Prospects of Low Dielectric Constant Materials
for ULSI Application Abst. IUMRS-ICAM Symposium B-1, Yokohama, 2003. K.
Endo
4. Amorphous Diamond Like Carbon Interlayer Dielectric Film for IC Application
The Application of Nano Crystalline Diamond like Carbon Materials, Kolkata,
2006. K. Endo
5. Fabrication and Power-Management Demonstration of Four-Terminal FinFETs
Electrochemical Society Meeting, Silicon on Insulator Technology and Devices
13, Chicago, 2007. K. Endo, Y. Liu, M. Masahara, T. Matsukawa, S. O’uchi,
and E. Suzuki
6. Fabrication and Issues of Double-Gate MOSFETs with Upstanding Channels
13th Workshop on Gate Stack Technology and Physics, Mishima, 2008. K. Endo
7. Independent Double-Gate FinFET SRAM Technology International Nanoelectronics
Conference, Tao-Yuan, 2011. K. Endo
8. Double-Gate CMOS Device Technology Fourth international symposium on
atomically controlled fabrication Technology, Osaka, 2011. K. Endo
9. Independent Double-Gate FinFET SRAM Technology Electrochemical Society
222nd Meeting, Dielectric Materials and Metals for Nanoelectronics and
Photonics 10, Honolulu, (2012). K. Endo
10. Recent Progress in Double Gate FinFET Technology The Energy Materials
Nanotechnology Meeting, Xian, 2012. K. Endo, S. O’uchi, T. Matsukawa, Y.
Liu, M. Masahara
11. Enhancing SRAM Performance by Advanced FinFET Device Technology Nanoscience
and Technology Conference, Qingdao, 2012. K. Endo
12. Advanced FinFET SRAM Technology Energy Materials Nanotechnology East
Meeting, Beijing, 2013. K. Endo
13. Enhancing SRAM Performance by Advanced FinFET Device and Circuit Technology
Collaboration for 14nm Node and Beyond 2013 Symposium on VLSI Technology,
Kyoto, 2013. K. Endo, S. O’uchi, T. Matsukawa, Y. Liu, K. Sakamoto, W.
Mizubayashi, S. Migita, Y. Morita, H. Ota, E. Suzuki, and M. Masahara
14. Advanced FinFET Device Technology for SRAM Applications International
Nanoelectoronics Conference, Sapporo, 2014. K. Endo
15. Variability in FinFET SRAM Cells 228th Electrochemcal Society Meeting,
Phenix, 2015. K. Endo, S. O’uchi, Y. Liu, T. Matsukawa, M. Masahara
16. Advanced FinFET Technologies for Boosting SRAM Performance IEEE 12th
International Conference on ASIC, Guiyang, China, 2017. K. Endo
17. Integration of Advanced Materials for Next Generation CMOS Nano Devices
International Conference on Emerging Advanced Nanomaterials, Newcastle,
Australia, 2018. K. Endo
18. Research on Post-Si devices based on Ge and 2D channel materials and
TCAD Simulation 22nd International Conference on Advanced Materials and
Simulation, Rome, 2018. K. Endo
19. Post-Si Nano Device Technology 2019 IEEE 13th International Conference
on ASIC (ASICON), Chongqing, 2019. K. Endo
20. Post Si Device and Process for Intelligent Nano Devices International
Electron Deivice and Materials Symposium, Hsinchu, 2020.K. Endo
論文
1. Treatment of the wall materials of extremely high vacuum chamber for
dynamical surface analysis Journal of Vacuum Science & Technology
A, 11, 1993, 417-421. K. Tsukui, R. Hasunuma, K. Endo, T. Osaka and I.
Ohdomari
2. Extremely high vacuum system for dynamical surface analysis Journal
of Vacuum Science & Technology A, 11, 1993, 2655-2658. K. Tsukui,
K. Endo, R. Hasunuma, T. Osaka, I. Ohdomari, N. Yagi and H. Aihara
3. Changes in transition temperature of the Si(111)1×1-7×7 phase transition
observed under various oxygen environments Surface Science, 328, 1995,
L553-560. K. Tsukui, K. Endo, R. Hasunuma, O. Hirabayashi, N. Yagi, H.
Aihara, T. Osaka and I. Ohdomari
4. Fluorinated amorphous carbon thin films grown by plasma enhanced chemical
vapor deposition for low dielectric constant interlayer dielectrics Journal
of Applied Physics, 78, 1995, 1370. 引用数153 (Web of Science)K. Endo and
T. Tatsumi
5. Fluorinated amorphous carbon thin films grown by helicon plasma enhanced
chemical vapor deposition for low dielectric constant interlayer dielectricsApplied
Physics Letters, 68, 1996, 2864-2866. 引用数98 (Web of Science)K. Endo and
T. Tatsumi
6. Nitrogen doped fluorinated amorphous carbon thin films grown by plasma
enhanced chemical vapor depositionApplied Physics Letters, 68 ,1996, 3656-3658.K.
Endo and T. Tatsumi
7. Effect of bias addition on the gap filling properties of fluorinated
amorphous carbon thin films grown by helicon wave plasma enhanced chemical
vapor deposition Japanese Journal of Applied Physics, 35 ,1996, L1348-1350K.
Endo, T. Tatsumi and Y. Matsubara
8. Plasma fluorination of polyimide thin films Journal of Vacuum Science
& Technology A, 15 ,1997, 3134-3127. K. Endo and T. Tatsumi
9. Deposition of silicon dioxide films on amorphous carbon films for low
dielectric constant interlayer dielectrics Applied Physics Letters, 70,1997,
1078-1079. K. Endo, T. Tatsumi and Y. Matsubara
10. Amorphous carbon thin films containing benzene rings for low dielectric
constant interlayer dielectrics Applied Physics Letters ,70, 1997, 2616-2618.
K. Endo and T. Tatsumi
11. Controlling fluorine concentration of fluorinated amorphous carbon
thin films for low dielectric constant interlayer dielectrics Japanese
Journal of Applied Physics, 36 ,1997, L1531-1533. K. Endo and T. Tatsumi
12. Application of fluorinated amorphous carbon thin films for low dielectric
constant interlayer dielectrics Japanese Journal of Applied Physics, 37
,1998, 1809-1814. K. Endo, T. Tatsumi, Y. Matsubara and T. Horiuchi
13. Plasma deposition of low-dielectric-constant fluorinated amorphous
carbon Journal of Applied Physics, 86 ,1999, 2739-2745. 引用数160 (Web of
Science) K Endo, K. Shinoda and T. Tatsumi
14. Metal organic atomic layer deposition of high-k gate dielectrics by
using plasma oxidation Japanese Journal of Applied Physics, 42, 2003, L685-687.
K. Endo and T. Tatsumi
15. Metal organic atomic layer deposition of metal silicate film for high-k
gate dielectrics Japanese Journal of Applied Physics, 43 ,2004, L1296-1298.
K. Endo and T. Tatsumi
16. Suppression of Charges in Al2O3 Gate Dielectric and Improvement of
MOSFET Performance by Plasma Nitridation IEICE Transactions on Electronics,
E87-C , 2004, 30-36. K. Manabe, K. Endo, S. Kamiyama, T. Iwamoto, T. Ogura,
N. Ikarashi, T. Yamamoto and T. Tatsumi
17. Dopant profiling in vertical ultrathin channels for double-gate MOSFETs
by using SNDM Applied Physics Letters, 85, 2004, 4139-4141. M. Masahara,
S. Hosokawa, T. Matsukawa, K. Endo, Y. Naito, H. Tanoue, and E. Suzuki
18. Device design consideration for Vth-controllable 4-terminal DG-MOSFET
Japanese Journal of Applied Physics, 44, 2005, 2351-2356. M. Masahara,
Y. Liu, K. Sakamoto, K. Endo, T. Sekigawa, T. Matsukawa, and E. Suzuki
19. Demonstration of Dopant Profiling in Ultrathin Channels of Vertical-type
Double-Gate Metal-Oxide-Semiconductor Field-Effect-Transistor by Scanning
Nonlinear Dielectric Microscopy Japanese Journal of Applied Physics, 44,
2005, 2400-2404. M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Sekigawa,
T. Matsukawa, and E. Suzuki
20. Work function controllability of metal gates made by interdiffusing
metal stacks with low and high work functions Microelectronic Engineering,
80, 2005, 284-287. T. Matsukawa, Y. Liu, M. Masahara, K. Ishii, K. Endo,
H. Yamauchi, E. Sugimata, H. Takashima, T. Higashino, E. Suzuki, and S.
Kanemaru
21. Electron Mobility in MultifinFET with a (111) Channel Surface Fabricated
by Orientation-Dependent Wet Etching Microelectronic Engineering, 80, 2005,
390-393. Y. Liu, E. Sugimata, M. Masahara, K. Endo, K. Ishii, T. Matsukawa,
H. Takashima, H. Yamauchi, and E. Suzuki
22. Demonstration, Analysis and Device Design Considerations for Independent
Double-Gate MOSFETs IEEE Trans. Electron Devices, 52 ,2005, 2046-2053.
M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa,
H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki
23. Fabrication of a Vertical-Channel Double-Gate Metal-Oxide-Semiconductor
Field-Effect Transistor Using a Neutral Beam Etching Japanese Journal of
Applied Physics, 45, 2006, L279-281. K. Endo, S. Noda, M. Masahara, T.
Ozaki, T. Kubota, S. Samukawa, Y. Liu, K. Ishii, Y. Ishikawa, E. Sugimata,
T. Matsukawa, H. Takashima, H. Yamauchi, and E. Suzuki
24. Deoxidization of Cu Oxide under Extremely Low Oxygen Pressure Ambient
Japanese Journal of Applied Physics, 45, 2006, L393-395. K. Endo, N. Shirakawa,
Y. Yoshida, S. Ikeda, T. Mino, E. Gofuku, and E. Suzuki
25. Investigation of N-Channel Triple-Gate Metal-Oxide-Semiconductor Field-Effect
Transistors on (100) Silicon On Insulator Substrate Japanese Journal of
Applied Physics, 45, 2006, 3097-3100. K. Endo, M. Masahara, Y. Liu, T.
Matsukawa, K. Ishii, E. Sugimata, H. Takashima, H. Yamauchi, and E. Suzuki
26. New Fabrication Technology of Fin Field Effect Transistors Using Neutral-Beam
EtchingJapanese Journal of Applied Physics, 45, 2006, 5513-5516. K. Endo,
S. Noda, T. Ozaki, S. Samukawa, M. Masahara, Y. Liu, K. Ishii, H. Takashima,
E. Sugimata, T. Matsukawa, H. Yamauchi, Y. Ishikawa, and E. Suzuki
27. Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology
IEEE Transactions on Electron Devices, 53 ,2006, 1826-1833 引用数30 (Web of
Science) K. Endo, S. Noda, M. Masahara, T. Kubota, T. Ozaki, S. Samukawa,
Y. Liu, K. Ishii, Y. Ishikawa, E. Sugimata, T. Matsukawa, H. Takashima,
H. Yamauchi, and E. Suzuki
28. Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor
field-effect-transistor with ultra-thin Si channel and self-aligned source
and drain Applied Physics Letters, 88, 2006, 072103. M. Masahara, Y. Liu,
K. Endo, T. Matsukawa, K. Sakamoto, K. Ishii, S. O’uchi, E. Sugimata, H.
Yamauchi, and E. Suzuki
29. Demonstration and analysis of accumulation-mode DG-MOSFET Japanese
Journal of Applied Physics, 45, 2006, 3079-3084. M. Masahara, K. Endo,
Y. Liu, T. Matsukawa, S. O’uchi, K. Ishii, E. Sugimata, and E. Suzuki
30. Experimental Study of Effective Carrier Mobility of Multi-Fin-Type
Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with (111)
Channel Surface Fabricated by Orientation-Dependent Wet Etching Japanese
Journal of Applied Physics, 45, 2006, 3084-3087. Y. Liu, E. Sugimata, K.
Ishii, M. Masahara, K. Endo, T. Matsukawa, H. Yamauchi, S. O’uchi, and
E. Suzuki
31. Optimum Gate Workfunction for Vth-controllable 4T-XMOSFET IEEE. Trans.
Nanotechnology, 5, 2006, 716-722. M. Masahara, S. O’uchi, Y. Liu, K. Sakamoto,
K. Endo, T. Matsukawa, T. Sekigawa, H. Koike, and E. Suzuki
32. Investigation of the TiN Gate Electrode with Tunable Work Function
and Its Application for FinFET Fabrication IEEE. Trans. Nanotechnology,
5, 2006, 723-730. Y. Liu, S. Kijima, E. Sugimata, M. Masahara, K. Endo,
T. Matsukawa, K. Ishii, K. Sakamoto, T. Sekigawa, H. Yamauchi, Y. Takanashi,
and E. Suzuki
33. Four-Terminal FinFETs Fabricated Using an Etch-Back Gate Separation
IEEE Trans. Nanotechnology, 6, 2007, 201-205. K. Endo, Y. Ishikawa, Y.
Liu, K. Ishii, T. Matsukawa, S. O’uchi, M. Masahara, E. Sugimata, J. Tsukada,
H. Yamauchi, and E. Suzuki
34. A Dynamical Power-Management Demonstration Using Four-Terminal Separated-Gate
FinFETsIEEE. Electron Device Letters, 28, 2007, 452-454. K. Endo, Y. Ishikawa,
Y. Liu, T. Matsukawa, S. O’uchi, K. Ishii, M. Masahara, J. Tsukada, H.
Yamauchi, T. Sekigawa, H. Koike, and E. Suzuki
35. Experimental Evaluation of Effects of Channel Doping on Characteristics
of FinFETs IEEE Electron Device Letters, 28, 2007, 1123-112. K. Endo, Y.
Ishikawa, Y. Liu, M. Masahara, T. Matsukawa, S. O’uchi, K. Ishii, H. Yamauchi,
J. Tsukada, and E. Suzuki
36. Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs
and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs With
Asymmetric Gate-Oxide Thicknesses IEEE. Electron Device Letters, 28, 2007,
517-519. Y. Liu, T. Matsukawa, K. Endo, M. Masahara, S. O’uchi, K. Ishii,
H. Yamauchi, J. Tsukada, Y. Ishikawa, and E. Suzuki
37. Fin-height controlled TiN-gate FinFET CMOS based on experimental mobility
Microelectronic Engineering, 84, 2007, 2101-2104. Y. Liu, T. Matsukawa,
K. Endo, M. Masahara, S. O’uchi, H. Yamauchi, K. Ishii, J. Tsukada, Y.
Ishikawa, K. Sakamoto, and E. Suzuki
38. Dual Metal Gate Transistors with Symmetrical Threshold Voltages Using
Work-Function-Tuned Ta/Mo Bilayer Metal Gates Japanese Journal of Applied
Physics, 4, 2008, 2428-2432. T. Matsukawa, Y. Liu, K. Endo, M. Masahara,
Y. Ishikawa, H. Yamauchi, J. Tsukada, K. Ishii, and E. Suzuki
39. Nitrogen Gas Flow Ratio and Rapid Thermal Annealing Temperature Dependences
of Sputtered Titanium Nitride Gate Work Function and Their Effect on Device
Characteristics Japanese Journal of Applied Physics, 47, 2008, 2433-2437.
Y. Liu, T. Hayashida, T. Matsukawa, K. Endo, M. Masahara, S. O’uchi, K.
Sakamoto, K. Ishii, J. Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, and
E. Suzuki
40. A Ta/Mo interdifusion dual metal gate technology for drivability enhancement
of FinFETs IEEE Electron Device Letters, 29, 2008, 618-620. T. Matsukawa,
K. Endo, Y. Liu, S. O’uchi, Y. Ishikawa, H. Yamauchi, J. Tsukada, K. Ishii,
M. Masahara, K. Sakamoto, and E. Suzuki
41. Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdifusion Dual
Metal-Gate Technology for Low-Operating-Power Application IEEE Trans. Electron
Devices 55, 2008, 2454-2461. T. Matsukawa, K. Endo, Y. Liu, S. O’uchi,
Y. Ishikawa, H. Yamauchi, J. Tsukada, K. Ishii, M. Masahara, K. Sakamoto,
and E. Suzuki
42. Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based
technology Solid-State Electronics, 52, 2008, 1694-1702. S. O’uchi, K.
Endo, M. Masahara, K. Sakamoto, Y. Liu, T. Matsukawa, T. Sekigawa, H. Koike,
{ and E. Suzuki
43. Enhancing Noise Margins of Fin-Type Field Effect Transistor Static
Random Access Memory Cell by Using Threshold Voltage-Controllable Flexible-
Pass-Gates Applied Physics Express, 2, 2009, 054502. K. Endo, S. O'uchi,
Y., Y. Liu, T. Matsukawa, M. Masahara, K. Sakamoto, J. Tsukada, K. Ishii,
H. Yamauchi, and E. Suzuki
44. Independent-Double-Gate FinFET SRAM for Leakage Current Reduction IEEE
Electron Device Letters, 30, 2009, 757-759. 引用数20 (Web of Science) K. Endo,
S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, T. Sakamoto, M. Masahara,
J. Tsukada, K. Ishii, K. Yamauchi, and E. Suzuki
45. Reduction of Moisture in Semiconductor Dry Process Equipment by Generating
Extremely Low Oxygen Ambience Japanese Journal of Applied Physics, 48,
2009, 08HH01. K. Endo, N. Shirakawa, Y. Yoshida, T. Iwase, and T. Mino
46. Vertical ultrathin-channel multigate MOSFETs: Technological challenges
and future developments IEEJ Trans. Electrical and Electronic Engineering,
4, 2009, 386-391. M. Masahara, Y. Liu, K. Endo, T. Matsukawa and E. Suzuki
47. Fluctuation Analysis of Parasitic Resistance in FinFETs with Scaled
Fin Thickness IEEE Electron Device Letters, 30, 2009, 407-409. T. Matsukawa,
K. Endo, Y. Ishikawa, H. Yamauchi, S. O’uchi, Y. Liu, J. Tsukada, K. Ishii,
K. Sakamoto, E. Suzuki, and M. Masahara
48. Metal-Gate FinFET Variation Analysis by Measurement and Compact Model
IEEE Electron Device Letters, 30, 2009, 556-558. S. O’uchi, T. Matsukawa,
T. Nakagawa, K. Endo, Y. Liu, T. Sekigawa, J. Tsukada, Y. Ishikawa, H.
Yamauchi, K. Ishii, E. Suzuki, H. Koike, K. Sakamoto, and M. Masahara
49. Dual Metal Gate FinFET Integration by Ta/Mo Diffusion Technology for
Vt Reduction and Multi-Vt CMOS Application Solid-State Electronics, 53,
2009, 701-705. T. Matsukawa, K. Endo, Y. Liu, S. O’uchi, Y. Ishikawa, H.
Yamauchi, J. Tsukada, K. Ishii, K. Sakamoto, E. Suzuki, and M. Masahara
50. Low Temperature, Beam-Orientation-Dependent, Lattice-Plane-Independent,
and Damage-Free Oxidation for Three-Dimensional Structure by Neutral Beam
Oxidation Japanese Journal of Applied Physics, 48, 2009, 04C007. M. Yonemoto,
T. Ikoma, K. Sano, K. Endo, T. Matsukawa, M. Masahara, S. Samukawa
51. A Comparative Study of Nitrogen Gas Flow Ratio Dependence on the Electrical
Characteristics of Sputtered Titanium Nitride Gate Bulk Planar Metal-Oxide-Semiconductor
Field-Effect Transistors and Fin-Type Metal-Oxide-Semiconductor Field-Effect
Transistors Japanese Journal of Applied Physics, 48, 2009, 05DC01. T. Hayashida,
Y. Liu, T. Matsukawa, K. Endo, S. O’uchi, K. Sakamoto, K. Ishii, J. Tsukada,
Y. Ishikawa, H. Yamauchi, E. Suzuki, A. Ogura, and M. Masahara
52. Variability Analysis of TiN Metal-Gate FinFETs IEEE Electron Device
Letters, 31, 2010, 546-548. 引用数57 (Web of Science) K. Endo, S. O’uchi,
Y. Ishikawa, Y. Liu, T. Matsukawa, T. Sakamoto, J. Tsukada, H. Yamauchi,
and M. Masahara
53. Variability Analysis of TiN FinFET SRAM Cells and its Compensation
by Independent-DG FinFETs IEEE Electron Device Letters, 31, 2010, 1095-1097.
K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, T. Sakamoto, J.
Tsukada, H. Yamauchi, and M. Masahra
54. Rigorous Design of 22-nm Node 4-Terminal SOifinFETs for Reliable Low
Standby Power Operation with Semi-empirical Parameters Journal of Semiconductor
Technology and Science, 10, 2010, 265-275. S. Cho, S. Ouchi, K. Endo, S.
Kim, I. Kang, M. Masahara, J. Harris, B. Park
55. Design of SOI FinFET on 32 nm technology node for low standby power
(LSTP) operation considering gate-induced drain leakage (GIDL) Solid-State
Electronics, 54, 2010 1060-1065. S. Cho, J. Lee, S. O'uchi, K. Endo, M.
Masahara, B. Park
56. Minimization of Gate-induced Drain Leakage by Controlling Gate Underlap
Length for Low-standby-power Operation of 20-nm-level Four-terminal Silicon-on-lnsulator
Fin-shaped Field Effect Transistor Japanese Journal of Applied Physics,
49, 2010, 024203. S. Cho, S. O'uchi, K. Endo, T. Matsukawa, K. Sakamoto,
L. Yongxun, B. Park, M. Masahara
57. Investigation of Thermal Stability of TiN Film Formed by Atomic Layer
Deposition Using Tetrakis (dimethylamino) titanium Precursor for Metal-Gate
Metal-Oxide-Semiconductor Field-Effect-Transistor Japanese Journal of Applied
Physics, 49, 2010, 04DA16. T. Hayashida, K. Endo, Y. Liu, T. Kamei, T.
Matsukawa, S. O’uchi, K. Sakamoto, J. Tsukada, Y. Ishikawa, H. Yamauchi,
A. Ogura, and M. Masahara
58. High-Performance Three-Terminal Fin Field-Effect Transistors Fabricated
by a Combination of Damage-Free Neutral-Beam Etching and Neutral-Beam Oxidation
Japanese Journal of Applied Physics, 49, 2010, 04DC17. A. Wada, K. Sano,
M. Yonemoto, K. Endo, T. Matsukawa, M. Masahara, S. Samukawa
59. Investigation of low-energy tilted ion implantation for fin-type double-gate
metal-oxide-semiconductor field-effect transistor extension doping Japanese
Journal of Applied Physics, 49, 2010, 04DC18. Y. Liu, T. Matsukawa, K.
Endo, S. O’uchi, K. Sakamoto, J. Tsukada, Y. Ishikawa, H. Yamauchi, and
M. Masahara
60. Nanoscale Wet Etching of Physical-Vapor-Deposition Titanium Nitride
and Its Application for Sub-30nm Gate Length FinFET Fabrication Japanese
Journal of Applied Physics, 49, 2010, 06GH18. Y. Liu, T. Kamei, K. Endo,
S. O’uchi, K. Sakamoto, T. Hayashida, Y. Ishikawa, T. Matsukawa, K. Sakamoto,
A. Ogura, and M. Masahara
61. Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate
Transistors-Part I: Modeling, Analysis, and Experimental Validation IEEE
Transactions on Electron Devices, 57, 2010, 2504-2514. H. F. Dadgour, K.
Endo, V. De, and K. Banerjee
62. Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate
Transistors-Part II: Implications for Process, Device, and Circuit Design
IEEE Transactions on Electron Devices, 57, 2010, 2515-2525. H. F. Dadgour,
K. Endo, V. De, and K. Banerjee
63. Fabrication of Four-Terminal Fin Field-Effect Transistors with Asymmetric
Gate-Oxide Thickness Using an Anisotropic Oxidation Process with a Neutral
Beam Applied Physics Express, 3, 2010, 096502. A. Wada, K. Endo, M. Masahara,
C. Huan, S. Samukawa
64. Design Optimization of FinFET Domino Logic Considering the Width Quantization
Property IEEE Transactions on Electron Devices, 57, 2010, 2934-2943. S.
H. Rasouli, K. Endo, H. F. Dadgour, H. Koike and K. Banerjee
65. Experimental Study of Physical-Vapor-Deposited Titanium Nitride Gate
with An n+-Polycrystalline Silicon Capping Layer and Its Application to
20 nm Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors
Japanese Journal of Applied Physics, 50, 2011, 04DC14. T. Kamei, Y. Liu,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida,
T. Matsukawa, K. Sakamoto, A. Ogura, and M. Masahara
66. Static Noise Margin Enhancement by Flex-Pass-Gate SRAM Electronics
and Communication in Japan, 94, 2011, 57. S. O’uchi, M. Masahara, K. Sakamoto,
K. Endo, Y. Liu, T. Matsukawa, T. Sekigawa, H. Koike and E. Suzuki
67. Grain-Orientation Induced Quantum Confinement Variation in FinFETs
and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital
Design IEEE Transactions on Electron Devices, 58, 2011, 2282-2292. S. H.
Rasouli, K. Endo, J. F. Chen, N. Singh, K. Banerjee
68. Low activation energy, high-quality oxidation of Si and Ge using neutral
beam Applied Physics Letters, 98, 2011, 203111. A. Wada, K. Endo, M. Masahara,
C.-H. Huang, S. Samukawa
69. Enhancement of FinFET Performance using 25-nm-thin Sidewall Spacer
grown by Atomic Layer Deposition Solid-State Electronics, 74, 2012, 13-18.
K. Endo, Y. Ishikawa, T. Matsukawa, Y. Liu, S. O’uchi, K. Sakamoto, J.
Tsukada, H. Yamauchi, and M. Masahara
70. A Correlative Analysis Between Characteristics of FinFETs and SRAM
Performance IEEE Transactions on Electron Devices, 59, 2012, 1345-1352.
K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, T. Sakamoto, J.
Tsukada, H. Yamauchi, and M. Masahara
71. Variability analysis of scaled crystal channel and poly-Si channel
FinFETs IEEE Transactions on Electron Devices, 59, 2012, 573-581. Y. Liu,
T. Kamei, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y.
Ishikawa, H. Hayashida, K. Sakamoto, A. Ogura, and M. Masahara
72. Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance
IEEE Transactions on Electron Devices, 59, 2012, 647-653. T. Hayashida,
K. Endo, Y. Liu, S. Ouchi, T. Matsukawa, W. Mizubayashi, S. Migita, Y.
Morita, H. Ota, H. Hashiguchi, D. Kosemura, T. Kamei, J. Tsukada, Y. Ishikawa,
H. Yamauchi, A. Ogura and M. Masahara
73. Demonstration of Split-Gate Type Tri-Gate Flash Memory with Highly
Suppressed Over-Erase IEEE Electron Device Letters, 33, 2012, 345-347.
T. Kamei, Y. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi
Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, and M. Masahara 74. Variability
Origins of Parasitic Resistance in FinFETs with Silicided Source/Drain
IEEE Electron Device Letters, 33, 2012, 474-476. T. Matsukawa, Y. Liu,
K. Endo, J. Tsukada, Y. Ishikawa, H. Yamauchi, S. O’uchi, K. Sakamoto,
M. Masahara
75. A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology IEICE Transactions
on Electronics, 95-C-4, 2012, 686-695. S. Ouchi, K. Endo, T. Matsukawa,
Y. Liu, T. Nakagawa, Y. Ishikawa, J. Tsukada, H. Yamauchi, T. Sekigawa,
H. Koike, K. Sakamoto, M. Masahara
76. Experimental Comparisons between Tetrakis(dimethylamino) titanium Precursor-Based
Atomic-Layer-Deposited and Physical-Vapor-Deposited Titanium-Nitride Gate
for High-Performance Fin-Type Metal-Oxide-Semiconductor Field-Effect Transistors
Japanese Journal of Applied Physics, 51, 2012, 04DA05. T. Hayashida, K.
Endo, Y. Liu, S. O’uchi, T. Matsukawa, W. Mizubayashi, S. Migita, Y. Morita,
H. Ota, H. Hashiguchi, D. Kosemura, T. Kamei, J. Tsukada, Y. Ishikawa,
H. Yamauchi, A. Ogura and M. Masahara
77. Fabrication of Floating-Gate Type Fin-Channel Double-Gate and Tri-Gate
Flash Memories and Comparative Study of Their Electrical Characteristics
Japanese Journal of Applied Physics, 51, 2012, 04DD03. Y. Liu, T. Kamei,
T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa,
H. Hayashida, K. Sakamoto, A. Ogura, and M. Masahara
78. Fabrication and Characterization of NOR-Type Tri-gate Flash Memory
with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation Japanese
Journal of Applied Physics, 51, 2012, 06FE19. T. Kamei, Y. Liu, T. Matsukawa,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida,
K. Sakamoto, A. Ogura, M. Masahara
79. Experimental study of floating-gate-type metal-oxide-semiconductor
capacitors with nanosize triangular cross-section tunnel areas for low
operating voltage flash memory application Japanese Journal of Applied
Physics, 51, 2012, 06FF01. Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S.
O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto,
A. Ogura, M. Masahara
80. Decomposition of On-Current Variability of nMOS FinFETs for Prediction
Beyond 20 nm IEEE Transactions on Electron Devices, 59, 2012, 2003-2010.
T. Matsukawa, Y. Liu, S. O’uchi, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa,
H. Ota, S. Migita, Y. Morita, W. Mizubayashi, K. Sakamoto, M. Masahara
81. Independent Double-Gate FinFET SRAM Technology IEICE Transactions on
Electronics, E96-C, 2013, 413-420. K. Endo, S. Ouchi, T. Matsukawa, Y.
Liu, and M. Masahara
82. Atomic Layer Deposition of SiO2 for the Performance Enhancement of
Fin Field Effect Transistors Japanese Journal of Applied Physics, 52, 2013,
116503. K. Endo, Y. Ishikawa, T. Matsukawa, Y. Liu, S. O’uchi, T. Sakamoto,
J. Tsukada, H. Yamauchi, and M. Masahara
83. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices
with Implications for Design and Reliability IEEE Trans. On Computer-Aided
Design of Integrated Circuits and Systems, 32, 2013, 1045-1058. C. Xu,
S. Kolluri, K. Endo and K. Banerjee
84. Suppression of threshold voltage variability of double-gate fin field-effect
transistors using amorphous metal gate with uniform work function Applied
Physics Letters, 102, 2013, 162104. T. Matsukawa, Y. Liu, W. Mizubayashi,
J. Tsukada, H. Yamauchi, K. Endo, Y. Ishikawa, S. O’uchi, H. Ota, S. Migita,
Y. Morita, M. Masahara
85. Gate Structure Dependence of Variability in Polycrystalline Silicon
Fin-Channel Flash Memories Japanese Journal of Applied Physics, 52, 2013,
06GE01. Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada,
H. Yamauchi, Y. Ishikawa, H. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
86. Influence of work function variation of metal gates on fluctuation
of sub-threshold drain current for fin field-effect transistors with undoped
channels Japanese Journal of Applied Physics 53 ,2014, 04EC11. T. Matsukawa,
Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O’uchi, W. Mizubayashi,
H. Ota, S. Migita, Y. Morita, M. Masahara
87. Experimental Study of Three-Dimensional Fin-Channel Charge Trapping
Flash Memories with Titanium Nitride and Polycrystalline Silicon Gates
Japanese Journal of Applied Physics, 53, 2014, 04ED16. Y. Liu, T. Matsukawa,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi,
Y. Morita, S. Migita, H. Ota, and M. Masahara
88. Performance enhancement of tunnel field-effect transistors by synthetic
electric field effect IEEE Electron Device Letters, 35, 2014, 792-794.
Y. Morita, T. Mori, S. Migita, W. Mizubayashi, H. Tanabe, K. Fukuda, T.
Matsukawa, K. Endo, S. O’uchi, Y. Liu, M. Masahara and H. Ota
89. Comparative Study of Charge Trapping Type SOI FinFET Flash Memories
with Different Blocking Layer Materials Journal of Low Power Electronics
and Applications, 4, 2014, 153-167. Y. Liu, T. Nabatame, Y. Matsukawa,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi,
Y. Morita, S. Migita, H. Ota, T. Chikyo, M. Masahara
90. Performance evaluation of parallel electric field tunnel field-effect
transistor by a distributed-element circuit model Solid-State Electronics,
102, 2014, 82-86. Y. Morita, T. Mori, S. Migita, W. Mizubayashi, H. Tanabe,
T. Fukuda, K. Endo, T. Matsukawa, S. O’uchi, Y. Liu, M. Masahara, H. Ota
91. Impact of granular work function variation in a gate electrode on low
frequency noise for fin field-effect transistors Applied Physics Express,
8, 2015, 044201. T. Matsukawa, K. Fukuda, Y. Liu, J. Tsukada, H. Yamauchi,
K. Endo, Y. Ishikawa, S. O’uchi, S. Migita, Y. Morita, W. Mizubayashi,
H. Ota, M. Masahara
92. Highly Vt tunable and low variability triangular fin-channel MOSFETs
on SOTB Micorelectronics Engineering, 147, 2015, 290-293. Y. Liu, T. Matsukawa,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi,
Y. Morita, S. Migita, H. Ota, and M. Masahara
93. Improvement of Epitaxial Channel Quality on Heavily Arsenic- and Boron-doped
Si Surfaces and Impact on Performance of Tunnel Field-Effect Transistor
Solid-State Electronics, 113, 2015, 173-178. Y. Morita, T. Mori, S. Migita,
W. Mizubayashi, T. Fukuda, K. Endo, T. Matsukawa, S. O’uchi, Y. Liu, M.
Masahara, H. Ota
94. Heated ion implantation for high-performance and highly reliable silicon-on-insulator
complementary metal–oxide–silicon fin field-effect transistors Japanese
Journal of Applied Physics, 54, 2015, 04DA06. W. Mizubayashi, H. Onoda,
Y. Nakashima, Y. Ishikawa, T. Matsukawa, K. Endo, Y. X. Liu, S. O’uchi,
J. Tsukada, H. Yamauchi, S. Migita, Y. Morita, H. Ota, and M. Masahara
95. Channel shape and interpoly dielectric material effects on electrical
characteristics of floating-gate-type three-dimensional fin channel flash
memories Japanese Journal of Applied Physics, 54, 2015, 04DD04. Y. Liu,
T. Nabatame, N. Nguyen, Y. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H.
Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T.
Chikyo, M. Masahara
96. Impact of fin length on threshold voltage modulation by back bias for
independent double-gate tunnel fin field-effect transistors Solid-State
Electronics, 111, 2015, 62-66. W. Mizubayashi, K. Fukuda, T. Mori, K. Endo,
Y. X. Liu, T. Matsukawa, S. O’uchi, Y. Ishikawa, S. Migita, Y. Morita,
A. Tanabe, J. Tsukada, H. Yamauchi, M. Masahara, H. Ota 97. Silicon nanodisk
array with a fin field-effect transistor for time-domain weighted sum calculation
toward massively parallel spiking neural networks Applied Physics Express,
9, 2016, 034201. T. Tohara, H. Liang, K. Tanaka, M. Igarashi, S. Samukawa,
K. Endo, Y. Takahashi, T. Morie
98. Introduction of SiGe/Si heterojunction into novel multilayer tunnel
FinFET Japanese Journal of Applied Physics, 55, 2016, 04EB06. Y. Morita,
K. Fukuda, T. Mori, W. Mizubayashi, S. Migita, K. Endo, Y. Liu, M. Masahara
and T. Matsukawa
99. Bias temperature instability in tunnel field-effect transistors Japanese
Journal of Applied Physics, 56, 2017, 04CA04. W. Mizubayashi, T. Mori,
K. Fukuda, Y. Ishikawa, Y. Morita, S. Migita, H. Ota, Y. Liu, S. Ouchi,
J. Tsukada, H. Yamauchi, T. Matsukawa, M. Masahara and K. Endo 100. On
the drain bias dependence of long channel silicon-oninsulator based tunnel
field effect transistors Japanese Journal of Applied Physics, 56, 2017,
04CD04. K. Fukuda, T. Mori, H. Asai, J. Hattori, W. Mizubayashi, Y. Morita,
Y. Fukuta, S. Migita, H. Ota, M. Masahara, K. Endo, T. Matsukawa
101. Tunnel FinFET CMOS inverter with very low short-circuit current for
ultralow-power Internet of Things application” Japanese Journal of Applied
Physics, 56, 2017, 04CD19. Y. Morita, K. Fukuda, Y. Liu, T. Mori, W. Mizubayashi,
S. Ouchi, H. Fuketa, S. Otsuka, S. Migita, M. Masahara, K. Endo, H. Ota
and T. Matsukawa 102. Impacts of plasma-induced damage due to UV light
irradiation during etching on Ge fin fabrication and device performance
of Ge fin field-effect transistors Applied Physics Express, 10, 2017, 026501.
W. Mizubayashi, S. Noda, Y. Ishikawa, T. Nishi, A. Kikuchi, H. Ota, P.
Su, Y. Li, S. Samukawa and K. Endo
103. CVD Growth Technologies of Layered MX2 Materials for Real LSI Applications
- Position and Growth Direction Control and Gas Source Synthesis IEEE Journal
of the Electron Devices Society, 6, 2018, 1159. T. Irisawa, N. Okada, W.
Mizubayashi, T. Mori, W. Chang, K. Koga, A. Ando, K. Endo, S. Sasaki, N.
Endo, Y. Miyata 104. Steep Switching in Trimmed-Gate Tunnel FET AIP Advances,
8, 2018, 095103 H. Asai, T. Mori, T. Matsukawa, J. Hattori, K. Endo, K.
Fukuda
105. A simulation study of short-channel effects of tunnel field-effect
transistors Japanese Journal of Applied Physics, 57, 2018, 04FD04. K. Fukuda,
H. Asai, J. Hattori, T. Mori, Y. Morita, W. Mizubayashi, M. Masahara, S.
Mitiga, H. Ota, K. Endo, T. Matsukawa
106. Enhancement of Capacitance Benet by Drain Offset Structure in TFET
Circuit Speed Associated with Tunneling Probability Increase Japanese Journal
of Applied Physics, 57, 2018, 04FD13. H. Asai, T. Moari, T. Matasukawa,
J. Hattori, K. Endo, T. Matsukawa
107. Atomic layer defect-free etching for germanium using HBr neutral beam
Journal of Vacuum Science & Technology A, 37, 2019, 051001. Takuya
Fujii, Daisuke Ohori, Shuichi Noda, Yosuke Tanimoto, Daisuke Sato, Hideyuki
Kurihara, Wataru Mizubayashi, Kazuhiko Endo, Yiming Li, Yao-Jen Lee, Takuya
Ozaki, and Seiji Samukawa
108. Steep switching less than 15 mV/dec in silicon-on-insulator tunnel
FETs by a trimmed-gate structure Japanese Journal of Applied Physics, 58,
2019, SBBA16. H. Asai, T. Mori, T. Matsukawa, J. Hattori, K. Endo, K. Fukuda
109. Atomic layer germanium etching for 3D Fin-FET using chlorine neutral
beam Journal of Vacuum Science & Technology A, 37, 2019, 021003
D. Ohori, T. Fujii, S. Noda, W. Mizubayashi, K. Endo, E.-T. Lee, Y. Li,
Y.-J. Lee, T. Ozaki, S. Samukawa
110. Quantification of Spin Drift in Devices with a Heavily Doped Si Channel
Physical Review Applied, 11, 2019, 044020 A. Spiesser, Y. Fujita, H. Saito,
S. Yamada, K. Hamaya, W. Mizubayashi, K. Endo, S. Yuasa, R. Jansen
111. Near‐Complete Elimination of Size‐Dependent Efficiency Decrease in
GaN Micro‐Light‐Emitting Diodes Physica Status Solidi (a), 216, 2019, 1900380.
J. Zhu, T. Takahashi, D. Ohori, K. Endo, S. Samukawa, M. Shimizu, X.-L.
Wang
112. Microwave Annealing Technologies for Variability Reduction of Nanodevices:
A Review of Their Impact on FinFETs IEEE Nanotechnology Magazine, 13, 2019,
34-38. K. Endo and Y.-J. Lee
113. The 2D Materials Used for Nanodevice Applications: Utilizing Aggressively
Scaled Transistors IEEE Nanotechnology Magazine, 13, 2019, 39-42. K. Endo,
Y. Miyata, and T. Irisawa
114. Performance improvement of Ge fin field-effect transistors by post-fin-fabrication
annealing Japanese Journal of Applied Physics, 59, 2020, SIIE05. W. Mizubayashi,
H. Oka, T. Mori, Y. Ishikawa, S. Samukawa, K. Endo
115. High-quality nanodisk of InGaN/GaN MQWs fabricated by neutral-beam-etching
and GaN regrowth: towards directional micro-LED in top-down structure Semiconductor
Science and Technology, 35, 2020, 075001. K. Zhang, T. Takahashi, D. Ohori,
G. Cong, K. Endo, N. Kumagai, S. Samukawa, M. Shimizu, X. Wang
116. High Electron Mobility Germanium FinFET Fabricated by Atomic Layer
Defect-Free and Roughness-Free Etching IEEE Open Journal of Nanotechnology,
2, 2021, 26-30. D. Ohori, T. Fujii, S. Noda, W. Mizubayashi, K. Endo, Y.-J.
Lee, J.-H. Tarng, Y. Li, S. Samukawa
117. Management of Phonon Transport in Lateral Direction for Gap-controlled
Si Nanopillar/SiGe Interlayer Composite Materials IEEE Open Journal of
Nanotechnology, 2, 2021, 148 -152. D. Ohori, M. Chuang, A. Sato, S. Takeuchi,
M. Murata, J. Yamamoto, M. Lee, K. Endo, Y. Li, J. Tarng, Y, Lee, S. Samukawa
118. Surface wettability of silicon nanopillar array structures fabricated
by biotemplate ultimate top-down processes Journal of Vacuum Science &
Technology A, 39, 2021, 023202. S. Takeuchi, D. Ohori, M. Sota, T. Ishida,
Y. Li, J.-H. Tarng, K. Endo, S. Samukawa
119. Non-equilibrium solid-phase growth of amorphous GeSn layer on Ge-on-insulator
wafer induced by flash lamp annealing Applied Physics Express, 14, 2021,
025505. H. Oka, W. Mizubayashi, Y. Ishikawa, N. Uchida, T. Mori, K. Endo
120. Flash Lamp Annealing Processing for the Performance Improvement of
High-Sn Content GeSn n-MOSFETs Applied Physics Express, 14, 2021, 096501.
H. Oka, W. Mizubayashi Y. Ishikawa, N. Uchida, T. Mori and K. Endo
121. Room-temperature and High-quality HfO2/SiO2 Gate Stacked Film Grown
by Neutral Beam Enhanced Atomic Layer Deposition Journal of Vacuum Science
& Technology A, 40, 2022, 022405. B. Ge, D. Ohori, Y. Chen, T.
Ozaki, K. Endo, Y. Li, J. Tarng, S. Samukawa
国際学会
1. Nitrogen doped fluorinated amorphous carbon thin films grown by plasma
enhanced chemical vapor deposition International Conference on Solid State
Device and Materials, Osaka, (1995), 3 pages. K. Endo and T. Tatsumi
2. Effect of bias addition on the gap filling properties of fluorinated
amorphous carbon thin films grown by helicon wave plasma enhanced chemical
vapor deposition International Conference on Solid State Device and Materials,
Yokohama, 1996, 3 pages. K. Endo and T. Tatsumi
3. Low-k fluorinated amorphous carbon interlayer technology for quarter
micron devices International Electron Device Meeting, San Francisco, 1996,
4 pages. Y. Matsubara, K. Endo, T. Tatsumi, H. Ueno, K. Sugai and T. Horiuchi
4. RC delay reduction of 0.18µm CMOS technology using low dielectric constant
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Francisco, 1998, 4 pages.Y. Matsubara, K. Kishimoto, K. Endo, M. Iguchi,
T. Tatsumi, H. Gomi, T. Horiuchi, E. Tzou, M. Xi, L. Y. Cheng, D. Tribula,
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Conference on Solid State Device and Materials, Tokyo, 2004, 2 pages. M.
Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Sekigawa, T. Matsukawa, and
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6. Dopant profiling in vertical ultrathin channel for DG-MOSFET by SNDM
International Conference on Solid State Device and Materials, Tokyo, 2004,
2 pages. M. Masahara, S. Hosokawa, T. Matsukawa, K. Endo, Y. Naito, and
E. Suzuki
7. Work function control of Al-Ni alloy for metal gate application International
Conference on Solid State Device and Materials, Tokyo, 2004, 2 pages. T.
Matsukawa, C. Yasumuro, H. Yamauchi, S. Kanemaru, M. Masahara, K. Endo,
E. Suzuki, and J. Ito
8. On the Vth controllability for 4T-DGFET International SOI Conference,
Charleston, 2004, 2 pages M. Masahara, Y. Liu, K. Sakamoto, K. Endo, K.
Ishii, T. Matsukawa, S. Hosokawa, T. Sekigawa, H. Tanoue, H. Yamauchi,
S. Kanemaru, and E. Suzuki
9. Investigation of N-Channel Triple-Gate MOSFETs on (100) SOI Substrate
International Conference on Solid State Device and Materials, Kobe, 2005,
2 pages. K. Endo, M. Masahara, Y. Liu, K. Ishii, E. Sugimata, H. Takashima,
H. Yamauchi, and E. Suzuki
10. Damage-Free Neutral Beam Etching Technology for High Mobility FinFETs
International Electron Device Meeting, Washington D. C., 2005, 4 pages
K. Endo, S. Noda, M. Masahara, T. Ozaki, T. Kubota, S. Samukawa, Y. Liu,
K. Ishii, Y. Ishikawa, E. Sugimata, T. Matsukawa, H. Takashima, H. Yamauchi,
and E. Suzuki
11. Demonstration and device design consideration of Vth-controllable independent
double-gate MOSFET (4T-XMOSFET) Electrochemical Society Meeting, Quebec,
2005, 2 pages M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa,
K. Ishii, T. Sekigawa, H. Koike, and E. Suzuki
12. TiN Gate Electrode with Tunable Work Function for FinFET Fabrication
Silicon Nanoelectronics Workshop, Kyoto, 2005, 2 pages. Y. Liu, S. Kijima,
E. Sugimata, M. Masahara, K. Endo, K. Ishii, T. Matsukawa, H. Takashima,
H. Yamauchi, Y. Takanashi, and E. Suzuki
13. Optimum Gate Workfunction for 4T-XMOSFET Silicon Nanoelectronics Workshop,
Kyoto, 2005, 2 pages M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa,
T. Sekigawa, and E. Suzuki
14. Work function control of metal gates by interdiffused Ni-Ta with high
thermal stability 35th European Solid-State Device Research Conference
(ESSDERC), Grenoble, 2005, 4 pages. T. Matsukawa, Y. Liu, M. Masahara,
K. Endo, K. Ishii, H. Yamauchi, E. Sugimata, H. Takashima, E. Suzuki, and
S. Kanemaru
15. Carrier Mobility in Multi-FinFETs with a (111) Channel Surface Fabricated
by Orientaion-Dependent Wet Etching International Conference on Solid State
Device and Materials, Kobe, 2005, 2 pages Y. Liu, E. Sugimata, K. Ishii,
M. Masahara, K. Endo, T. Matsukawa, H. Yamauchi, and E. Suzuki
16. Comparative study on effective electron mobility in FinFETs with a
(111) channel surface fabricated by wet and dry etching processes Microprocess
and Nanotechnology Conference, Tokyo, 2005, 2 pages. Y. Liu, E. Sugimata,
M. Masahara, K. Ishii, K. Endo, T. Matsukawa, H. Yamauchi, and E. Suzuki
17. Advanced FinFET Technology: TiN Metal-gate CMOS and 3T/4T Device Integration
IEEE International SOI Conference, Honolulu, 2005, 2 pages. Y. Liu, K.
Endo, M. Masahara, E. Sugimata, T. Matsukawa, K. Ishii, H. Yamauchi, T.
Shimizu, S. O’uchi, T. Sekigawa, and E. Suzuki
18. An Experimental Study on the Thermal Stability of Sputtered TiN Gates
for Gate-first FinFETs International Semiconductor Device Research Symposium,
TP6-02, Bethesda, 2005, 2 pages. Y. Liu, E. Sugimata, T. Matsukawa, M.
Masahara, K. Endo, K. Ishii, T. Shimizu, and E. Suzuki
19. A Dynamical Power-Management Demonstration Using Four-Terminal Separated-Gate
FinFETs IEEE International SOI Conference, Honolulu, 2006, 2 pages. K.
Endo, Y. Ishikawa, Y. Liu, T. Matsukawa, S. O’uchi, K. Ishii, M. Masahara,
J. Tsukada, and E. Suzuki
20. Advanced TiN Metal-Gate FinFET Technology The Electrochemical Society
Meeting, Denver, 2006, 13 pages. Y. Liu, E. Sugimata, T. Matsukawa, M.
Masahara, K. Endo, K. Ishii, T. Shimizu, H. Yamauchi, S. O’uchi, and E.
Suzuki 21. Four-Terminal Double-Gate Logic for LSTP Applications below
32-nm Technology Node International Conference on Integrated Circuit Design
and Technology, Padova, Italy, 2006, 4 pages. S. O’uchi, Y. Liu, M. Masahara,
T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, and
E. Suzuki
22. Low-Leakage-Current Ultrathin SiO2 Film by Low-Temperature Neutral
Beam Oxidation International Conference on Solid State Device and Materials,
Yokohama, 2006, 2 pages. A. Ikoma, T. Taguchi, S. Fukuda, K. Endo, H. Watanabe,
and S. Samukawa
23. Ta/Mo Stack Dual Metal Gate Technology Applicable to Gate-First Processes
International Conference on Solid State Device and Materials, Yokohama,
2006, 2 pages T. Matsukawa, Y. Liu, K. Endo, M. Masahara, K. Ishii, S.
O’uchi, H. Yamauchi, J. Tsukada and E. Suzuki
24. Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric
Gate Insulator Thickness 4T-FinFETs International Electron Device Meeting,
San Francisco, 2006, 4 pages. Y. Liu, T. Matsukawa, K. Endo, M. Masahara,
K. Ishii, S. O’uchi, H. Yamauchi, J. Tsukada, Y. Ishikawa, and E. Suzuki
25. TiN Gate Work Function Control Using Nitrogen Gas Flow Ratio and RTA-Temperature
International Conference on Solid State Device and Materials, Tsukuba,
2007, 2 pages Y. Liu, T. Hayashida, T. Matsukawa, K. Endo, M. Masahara,
S. O’uchi, K. Sakamoto, K. Ishii, J. Tsukada, Y. Ishikawa, H. Yamauchi,
A. Ogura, and E. Suzuki
26. Dual Metal Gate MOSFETs with Symmetrical Threshold Voltages Using Work
Function Tuned Ta/Mo Bi-layer Metal Gates International Conference on Solid
State Device and Materials, Tsukuba, 2007, 2 pages. T. Matsukawa, Y. Liu,
K. Endo, M. Masahara, Y. Ishikawa, H. Yamauchi, J. Tsukada, K. Ishii, and
E. Suzuki
27. Advanced DG-MOSFETs Process Technologies 5th Symposium on ULSI Process
Integration, 212th Meeting of the Electrochemical Society, Washington D.C.,
2007, 11 pages. E. Suzuki, Y. Liu, K. Endo, T. Matsukawa, M. Masahara,
K. Sakamoto, and S. O’uchi
28. Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using
FinFET-Based Technology IEEE Custom Integrated Circuits Conference, Santa
Clara, 2007, 4 pages. S. O’uchi, M. Masahara, K. Sakamoto, K. Endo, Y.
Liu, T. Matsukawa, T. Sekigawa, H. Koike, and E. Suzuki
29. A Ta/Mo Interdiffusion Gate Technology for Dual Metal Gate First FinFET
Fabrication IEEE International SOI Conference, Palm Springs, 2007, 2 pages.
T. Matsukawa, K. Endo, Y. Liu, S. O’uchi, Y. Ishikawa, H. Yamauchi, J.
Tsukada, K. Ishii, M. Masahara, K. Sakamoto, and E. Suzuki
30. Nitrogen Gas Flow Ratio Controlled PVD TiN Metal Gate Technology for
FinFET CMOS International Semiconductor Device Research Symposium, WP9-06,
College Park, 2007, 2 pages. Y. Liu, T. Hayashida, T. Matsukawa, K. Endo,
M. Masahara, S. O’uchi, K. Sakamoto, K. Ishii, J. Tsukada, Y. Ishikawa,
H. Yamauchi, A. Ogura, E. Suzuki
31. Modeling and Analysis of Self-Heating in FinFET Devices for Improved
Circuit and EOS/ESD Performance International Electron Device Meeting,
Washington D.C., 2007, 4 pages. S. Kolluri, K. Endo, E. Suzuki, and K.
Banerjee
32. Independent-Gate Four-Terminal FinFET SRAM for Drastic Leakage Current
Reduction International Conference on IC Design and Technology, Grenoble,
2008, 4 pages. K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K.
Sakamoto, M. Masahara, J. Tsukada, K. Ishii, H. Yamauchi, and E. Suzuki
33. Enhancing Noise Margins of FinFET SRAM by Integrating Vth-Controllable
Flexible-Pass-Gates 38th European Solid State Device Research Conference,
Edinburgh, 2008, 4 pages. K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa,
M. Masahara, K. Sakamoto, J. Tsukada, K. Ishii, H. Yamauchi, and E. Suzuki
34. Enhancing SRAM Cell Performance by Using Independent Double-Gate FinFET
International Electron Device Meeting, San Francisco, 2008, 4 pages. K.
Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K. Sakamoto, J. Tsukada,
K. Ishii, H. Yamauchi, E. Suzuki, and M. Masahara
35. Variable-Threshold-Voltage FinFETs with a Control-Voltage Range within
the Logic-Level Swing Using Asymmetric Work-Function Double Gates International
Symposium on VLSI Technology, Systems and Applications, Hshinchu ,2008,
2 pages. S. O’uchi, K. Sakamoto, K. Endo, M. Masahara, T. Matsukawa, Y.
Liu, M. Hioki, T. Nakagawa, T. Sekigawa, H. Koike, and E. Suzuki
36. An Experimental Study of TiN Gate FinFET SRAM with (111)-Oriented S
idewall Channels Silicon Nanoelectronis Workshop, Honolulu, 2008, 2 pages.
Y. Liu, T. Hayashida, T. Matsukawa, K. Endo, S. O’uchi, K. Sakamoto, M.
Masahara, K. Ishii, J. Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, and
E. Suzuki
37. Dual Metal Gate FinFET Integration by Ta/Mo Diffusion Technology for
Vt Reduction and Multi-Vt CMOS Application 38th European Solid-State Device
Research Conference, Edinburgh, 2008, 4 pages. T. Matsukawa, K. Endo, Y.
Liu, S. O’uchi, M. Masahara, Y. Ishikawa, H. Yamauchi, J. Tsukada, K. Ishii,
K. Sakamoto, and E. Suzuki 38. Low Temperature, Anisotropic, Lattice-Plane-Free
and Damage-free Oxidation for 3 Dimensional Structure by Oxygen Neutral
Beams International Conference on Solid State Device and Materials, Tsukuba,
2008, 2 pages. M. Yonemoto, K. Sano, K. Endo, T. Matsukawa, M. Masahara
and S. Samukawa
39. Advanced Metal Gate FinFET CMOS Technology 213th Electrochemical Society
Meeting, Phoenix, 2008, 14 pages. Y. Liu, T. Matsukawa, K. Endo, M. Masahara,
S. O’uchi, K. Ishii, K. Sakamoto, E. Suzuki
40. Impact of Extension and Source/Drain Resistance on FinFET Performance
IEEE International SOI Conference, New York, 2008, 2 pages. T. Matsukawa,
K. Endo, Y. Ishikawa, H. Yamauchi, Y. Liu, S. O’uchi, J. Tsukada, K. Ishii,
K. Sakamoto, E. Suzuki, and M. Masahara
41. Logic Gate Threshold Voltage Controllable Single Metal Gate FinFET
CMOS Inverters Implemented by Using Co-integration of 3T/4T-FinFETs IEEE
International SOI Conference, New York, 2008, 2 pages. Y. Liu, T. Sekigawa,
T Hayashida, T. Matsukawa, K. Endo, S. O’uchi, K. Sakamoto, K. Ishii, J.
Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, H. Koike, E. Suzuki, and M.
Masahara
42. Demonstration Gate Work Function Engineered FinFET CMOS International
Workshop on Dielectric Thin Films for Future Electron Devices, Tokyo, 2008,
2 pages. Y. Liu, T. Hayashida T. Matsukawa, K. Endo, S. O’uchi, K. Sakamoto,
J. Tsukada, K. Ishii, Y. Ishikawa, H. Yamauchi, A. Ogura, E. Suzuki, M.
Masahara
43. A Comparative Study of the Electrical Characteristics of Sputtered
TiN Gate Planar MOSFETs and FinFETs International Workshop on Dielectric
Thin Films for Future Electron Devices, Tokyo, 2008, 2 pages T. Hayashida,
Y. Liu, T. Matsukawa, K. Endo, S. O’uchi, K. Sakamoto, J. Tsukada, K. Ishii,
Y. Ishikawa, H. Yamauchi, A. Ogura, E. Suzuki, and M. Masahara 44. Dual
Metal Gate Integration for CMOS FinFETs using Selective Formation of Ta/Mo
Interdiffused GateInternational Workshop on Dielectric Thin Films for Future
Electron Devices, Tokyo, 2008, 2 pages.T. Matsukawa, K. Endo, Y. Ishikawa,
H. Yamauchi, Y. Liu, J. Tsukada, K. Ishii, S. O’uchi, K. Sakamoto, E. Suzuki,
and M. Masahara
45. Characterization of Metal-Gate FinFET Variability Based on Measurements
and Compact Model Analyses International Electron Devices Meeting, San
Francisco, 2008, 4 pages. S. O’uchi, T. Matsukawa, T. Nakagawa, K. Endo,
Y. Liu, T. Sekigawa, J. Tsukada, Y. Ishikawa, H. Yamauchi, K. Ishii, E.
Suzuki, H. Koike, and M. Masahara
46. Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate
Devices and Implications for SRAM Reliability International Electron Device
Meeting, San Francisco, 2008, 4 pages H. Dadgour, K. Endo, V. De, and K.
Banerjee
47. Variation Analysis of TiN FinFETs International Semiconductor Device
Research Symposium, Maryland, 2009, 2 pages. K. Endo, T. Matsukawa, Y.
Ishikawa, Y. Liu, S. O’uchi, K. Sakamoto, J. Tsukada, H. Yamauchi, and
M. Masahara
48. Minimization of Gate-Induced Drain Leakage (GIDL) for Low Standby Power
in 20 nm Level SOI 4-T FinFETs by Controlling Underlap Lengths Silicon
Nanoelectroics Workshop, Kyoto, 2009, 2 pages. S. Cho, S. O’uchi, K. Endo,
T. Matsukawa, K. Sakamoto, Y. Liu, B. Park, and M. Masahara
49. Comprehensive Analysis of Variability Sources of FinFET Characteristics
2009 Symposium on VLSI Technology, Kyoto, 2009, 2 pages. T. Matsukawa,
S. O’uchi, K. Endo, Y. Ishikawa, H. Yamauchi, Y. Liu, J. Tsukada, K. Sakamoto,
and M. Masahara
50. Impact of FinFET Technology on 6T-SRAM Performance IEEE International
SOI Conference, Foster City, 2009, 2 pages. S. O’uchi, T. Nakagawa, T.
Matsukawa, Y. Liu, K. Endo, T. Sekigawa, K. Sakamoto, H. Koike, and M.
Masahara
51. Rigorous Design of 20 nm Level SOI 4-T FinFETs for Low Standby Power
by Extracting Parameters from the Pre-stage 50 nm Technology Node Devices
International Conference on Solid State Device and Materials, Sendai, 2009,
2 pages. S. Cho, S. Kim, K. Endo, S. O’uchi, T. Matsukawa, K. Sakamoto,
Y. Liu, B. Park, and M. Masahara
52. Superiority of ALD TiN with TDMAT Precursor for Metal-Gate MOSFET International
Conference on Solid State Device and Materials, Sendai, 2009, 2 pages.
H. Hayashida, K. Endo, Y. Liu, T. Matsukawa, S. O’uchi, K. Sakamoto, J.
Tsukada, H. Yamauchi, A. Ogura, and M. Masahara
53. High-Performance three-terminal FinFETs by Combination of Damage-Free
Neutral-Beam Etching and Neutral-Beam Oxidation Technologies International
Conference on Solid State Device and Materials, Sendai, 2009, 2 pages Y.
Sano, M. Yonemoto, A. Wada, K. Endo, T Matsukawa, M. Masahara, and S. Samukawa
54. Investigation of low-energy tilted ion implantation for FinFET Extension
doping International Conference on Solid State Device and Materials, Sendai,
20
09, 2 pages Y. Liu, T. Matsukawa, K. Endo, S. O’uchi, K. Sakamoto, J. Tsukada,
Y. Ishikawa, H. Yamauchi, and M. Masahara 55. Design of SOI FinFET on 32
nm Technology Node for Low Standby Power (LSTP) Operation considering Gate-Induced
Drain Leakage (GIDL) International Semiconductor Device Research Symposium,
College Park, 2009, 2 pages. S. Cho, J. Lee, B. Park, S. O’uchi, K. Endo,
and M. Masahara
56. Nanoscale TiN Wet Etching and Its Application for FinFET Fabrication
International Semiconductor Device Research Symposium, College Park, 2009,
2 pages. Y. Liu, T. Kamei, K. Endo, S. O’uchi, J. Tsukada, H. yamauchi,
T. Hayashida, Y. Ishikawa, T. Matsukawa, J. Sakamoto, A. Ogura, and M.
Masahara
57. Variability Analysis of TiN FinFET SRAM Cell Performance and its Compensation
Using Vth-controllable Independent Double-Gate FinFET International Symposium
on VLSI Technology, Systems and Applications, Hsinchu, 2010, 2 pages. K.
Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K. Sakamoto, J. Tsukada,
H. Yamauchi, and M. Masahara
58. Advanced FinFET Technologies: Extension Doping, Vth Controllable CMOS
Inverters and SRAM The Electrochememical Society Meeting, Vancouver, 2010,
2 pages. Y. Liu, K. Endo, S. Ouchi, T. Matsukawa, K. Sakamoto, M. Masahra
59. On the Gate-Stack Origin Threshold Voltage Variability in Scaled FinFETs
and Multi-FinFETs2010 Symposium on VLSI Technology, Honolulu, 2010, 2 pages.
Y. Liu, K. Endo, S. Ouchi, T. Kamei, J. Tsukada, H. Yamauchi, Y. Ishikawa,
T. Hayashida, K. Sakamoto, T. Matsukawa, A. Ogura, M. Masahara
60. Fin-Height Controlled PVD-TiN Gate FinFET SRAM for Enhancing Noise
Margin 40th European Solid-State Device Research Conference, Sevilla, 2010,
4 pages. Y. Liu, K. Endo, S. O’uchi, T. Kamei, J. Tsukada, H. Yamauchi
61. 0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging
malfunctioned bits 36th European Solid-State Circuits Conference, Sevilla,
2010, 4 pages S. O’uchi, K. Endo, Y. Liu, T. Nakagawa, T. Matsukawa, Y.
Ishikawa, J. Tsukada, H. Yamauchi, T. Sekigawa, H. Koike, K. Sakamoto,
and M. Masahara
62. Realization of 0.7-V Analog Circuits by Adaptive-Vt Operation of FinFET
IEEE Custom Integrated Circuits Conference, San Jose, 2010, 4 pages. S.
O’uchi, K. Endo, E. Suzuki, Y. Liu, T. Matsukawa, Y. Ishikawa, J. Tsukada,
T. Sekigawa, H. Koike, K. Sakamoto and M. Masahara
63. Experimental Study of PVD-TiN Gate with Poly-Si Capping and Its Application
to 20 nm FinFET Fabrication International Conference on Solid State Device
and Materials, Tokyo, 2010, 2 pages. T. Kamei, Y. Liu, K. Endo, S. O’uchi,
J. Tsukada, H. Yamauchi, Y. Ishikawa, H. Hayashida, T. Matsukawa, K. Sakamoto,
A. Ogura and M. Masahara
64. Optimization of RTA process for PVD-TiN gate FinFETs IEEE International
SOI Conference, San Diego, 2010, 2 pages. Y. Liu, T. Kamei, K. Endo, S.
O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, T. Matsukawa,
K. Sakamoto, A. Ogura, and M. Masahara
65. High-Frequency Characterization of Intrinsic FinFET Channel IEEE International
SOI Conference, San Diego, 2010, 2 pages. H. Sakai, Y. O’uchi, T. Matsukawa,
K. Endo, Y. Liu, J. Tsukada, Y. Ishikawa, H. Nakagawa, T. Sekigawa, H.
Koike, K. Sakamoto, M. Masahara and H. Ishiguro
66. May the Fourth (terminal) be with you - Circuit Design beyond FinFET
International Electron Device Meeting, San Francisco, 2010, 1 page. H.
Koike, S. O’uchi, M. Hioki, K. Endo, T. Matsukawa, Y. Liu, M. Masahara,
T. Tsutsumi, K. Sakamoto, T. Nakagawa, T. Sekigawa
67. Atomic Layer Deposition of 25-nm-thin Sidewall Spacer for Enhancement
of FinFET Performance 41th European Solid State Device Research Conference,
Helsinki, 2011, 4 pages. K. Endo, Y. Ishikawa, T. Matsukawa, Y. Liu, S.
O’uchi, K. Sakamoto, J. Tsukada, H. Yamauchi, and M. Masahara
68. Correlative analysis between characteristics of 30-nm LG FinFETs and
SRAM performance International Electron Device Meeting, Washington D.C.,
2011, 4 pages. K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K.
Sakamoto, J. Tsukada, H. Yamauchi, and M. Masahara
69. Influence of NiSi on Parasitic Resistance Fluctuation of FinFETs Proceedings
of Technical Program, International Symposium on VLSI Technology, Systems
and Applications, Hsinchu, 2011, 2 pages. T. Matsukawa, Y. Liu, K. Endo,
J. Tsukada, Y. Ishikawa, H. Yamauchi, S. O’uchi, K. Sakamoto, and M. Masahara
70. Variability analysis of scaled poly-Si channel FinFETs and Tri-gate
flash memories for high density and low cost stacked 3D-memory application
41st European Solid-State Device Research Conference, Helsinki, 2011, 4
pages. Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada,
H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, and M. Masahara
71. Influence of Fin Height on Poly-Si/PVD-TiN Stacked Gate FinFET Performance
IEEE International SOI Conference, Tempe, 2011, 2 pages. T. Hayashida,
T. Kamei, K. Endo, Y. Liu, S. O’uchi T. Matsukawa, W. Mizubayashi, S. Migita,
Y. Morita, H. Ota, Y. Ishikawa, J. Tsukada, H. Yamauchi, and M. Masahara
72. Comparative Study of Tri-gate Flash Memories with Split and Stack Gates
IEEE. International SOI Conference, Tempe, 2011, 2 pages. T. Kamei, Y.
Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa,
T. Hayashida, K. Sakamoto, A. Ogura, and M. Masahara
73. Direct Comparison of Electrical Characteristics for Double-Gate and
Tri-Gate Flash Memories International Conference on Solid State Device
and Materials, Nagoya, 2011, 2 pages. Y. Liu, T. Kamei, T. Matsukawa, K.
Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K.
Sakamoto, A. Ogura, and M. Masahara
74. High Quality Germanium Dioxide Formation using Damage-Free and Low-temperature
Neutral Beam Oxidation Process International Conference on Solid State
Device and Materials, Nagoya, 2011, 2 pages. A. Wada, K. Endo, M. Masahara,
and S. Samukawa
75. Performance and Variability Comparisons between ALD- and PVD-TiN Gate
FinFET International Conference on Solid State Device and Materials, Nagoya,
2011, 2 pages. T. Hayashida, T. Kamei, K. Endo, Y. Liu, S. O’uchi T. Matsukawa,
W. Mizubayashi, S. Migita, Y. Morita, H. Ota, Y. Ishikawa, J. Tsukada,
H. Yamauchi, and M. Masahara
76. Advanced FinFET Process Technology for 20 nm Node and Beyond International
Nanoelectronics Conference, Hsinchu, 2011, 2 pages. M. Masahara, T. Matsukawa,
K. Endo, Y. Liu, W. Mizubayashi, S. Migita, S. O’uchi, H. Ota, M. Morita
77. Demonstration of ALD-TiN Gate FinFET with TDMAT Precusor for WFV Reduction
Microprocess and Nanotechnology Conference, Kyoto, 2011, 2 pages. T. Hayashida,
T. Kamei, K. Endo, Y. Liu, S. O’uchi, T. Matsukawa, W. Mizubayashi, S.
Migita, Y. Morita, H. Ota, Y. Ishikawa, J. Tsukada, H. Yamauchi and M.
Masahara
78. Tri-gate flash memory with improved IPD layer Microprocesses and Nanotechnology
Conference, Kyoto, 2011, 2 pages. T. Kamei, Y. Liu, T. Matsukawa, K. Endo
S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto,
A. Ogura, and M. Masahara
79. Fabrication and characterization of floating-gate type MOS capacitors
with nanoscale triangular cross-section tunnel areas Microprocesses and
Nanotechnology Conference, Kyoto, 2011, 2 pages. Y. Liu, T. Kamei, T. Matsukawa,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida,
K. Sakamoto, A. Oguea, and M. Masahara
80. Comprehensive Analysis of Ion Variation in Metal Gate FinFETs for 20nm
and Beyond International Electron Devices Meeting, Washington D.C., 2011,
4 pages. T. Matsukawa, Y. Liu, S. O’uchi, K. Endo, J. Tsukada, H. Yamauchi
Y. Ishikawa, H. Ota, S. Migita, Y. Morita, W. Mizubayashi, K. Sakamoto,
and M. Masahara
81. Flexible Vth FinFETs with 9-nm-Thick Extremely-Thin BOX IEEE International
SOI Conference, Napa, 2012, 2 pages. K. Endo, S. Migita, Y. Ishikawa, Y.
Liu, T. Matsukawa, S. O’uchi, J. Tsukada, W. Mizubayashi, Y. Morita, H.
Ota, H. Yamauchi, M. Masahara.
82. On-current variability sources of FinFETs: Analysis and Perspective
for 14nm-Lg Technology 221st Electrochem. Soc. Meeting, Seattle, 2012,
13 pages. T. Matsukawa, Y. Liu, K. Endo, S. O’uchi, M. Masahara
83. FinFET Flash Memory Technology 221st Electrochem. Soc. Meeting, Seattle,
2012, 23 pages. Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O’uchi, J.
Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Oguea,
and M. Masahara
84. Comparative Study of Tri-Gate-and Double-Gate-Type Poly-Si Fin-Channel
Split-Gate Flash Memories Silicon Nanoelectronics Workshop, Honolulu, 2012,
2 pages Y. Liu, T. Kamei, M. Matsukawa, K. Endo, S. O’uchi, J. Tsukada,
H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
85. 1/f Noise Characteristic in Independent-Double-Gate-FinFET International
Conference on Solid State Devices and Materials, Kyoto, 2012, 2 pages.
H. Sakai, S. O’uchi, K. Endo, T. Matsukawa, Y. Liu, Y. Ishikawa, J. Tsukada,
T. Nakagawa, T. Sekigawa, H. Koike, M. Masahra, H. Ishiguro
86. Cryogenic Operation of Double-Gate FinFET and Demonstration of Analog
Circuit at 4.2K IEEE International SOI Conference, Napa, 2012, 2 pages.
S. Ouchi, K. Endo, T. Maezawa, T. Nakagawa, H. Ota, Y. Liu, T. Matsukawa,
Y. Ishikawa, J. Tsukada, H. Yamauchi, W. Mizubayashi, S. Migita, Y. Morita,
T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara
87. Experimental Study of SOI-FinFET Tri-Gate Flash Memoriy IEEE. International
SOI Conference, Napa, 2012, 2 pages. Y. Liu, T. Kamei, T. Matsukawa, K.
Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K.
Sakamoto, A. Ogura, and M. Masahara
88. Gate Structure Dependence of Variability in Poly-Si FinFET Flash Memories
Microprocesses and Nanotechnology Conference, Kobe, 2012, 2 pages. Y. Liu,
T. Kamei, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y.
Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
89. Suppressing Vt and Gm Variability of FinFETs Using Amorphous Metal
Gates for 14nm and Beyond International Electron Device Meeting, San Francisco,
2012, 4 pages. T. Matsukawa, Y. Liu, W. Mizubayashi, J. Tsukada, H. Yamauchi,
K. Endo, Y. Ishikawa, S. O’uchi, H. Ota, S. Migita, Y. Morita, M. Masahara
90. Analysis of Vth Flexibility in Ultrathin-BOX SOI FinFETs IEEE International
SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Monterey,
2013, 2 pages. K. Endo, S. O’uchi, T. Matsukawa, Y. Liu, K. Sakamoto, W.
Mizubayashi, S. Migita, Y. Morita, H. Ota, E. Suzuki, and M. Masahara
91. Suppressed Variability of Current-Onset Voltage of FinFETs by Improvement
of Work Function Uniformity of Metal Gates International Symposium on VLSI
Technology, Systems and Applications, Hsinchu, 2013, 2 pages. T. Matsukawa,
Y. Liu, K. Endo, W. Mizubayashi, J. Tsukada, Y. Ishikawa, H. Yamauchi,
S. O’uchi, H. Ota, S. Migita, Y. Morita, M. Masahara 92. Analysis of Threshold
Voltage Shifts in Double Gate Tunnel FinFETs: Effects of Improved Electrostatics
by Gate Dielectrics and Back Gate Effects International Symposium on VLSI
Technology, Systems and Applications, Hsinchu, 2013, 2 pages. W. Mizubayashi,
K. Fukuda, T. Mori, K. Endo, Y. Liu, T. Matsukawa, S. O’uchi, Y. Ishikawa,
S. Migita, Y. Morita, T. Tanabe, J. Tsukada, H. Yamauchi, M. Masahra, H.
Ota
93. Comparative Study of TiN Metal Gate and Poly-Si Gate Charge-Trapping
Type FinFET Flash Memories Silicon Nanoelectronics Workshop, Kyoto, 2013,
2 pages. Y. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi,
Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, M. Masahara
94. Synthetic electric field tunnel FETs: drain current multiplication
demonstrated by wrapped gate electrode around ultrathin epitaxial channel
2013 Symposium on VLSI Technology, Kyoto, 2013, 2 pages. Y. Morita, T.
Mori, S. Migita, W. Mizubayashi, T. Tanabe, K. Fukuda, T. Matsukawa, K.
Endo, S. O’uchi, Y. Liu, M. Masahara, H. Ota
95. CMOS-Compatible Mesa-Etched Ultrathin Epitaxial Channel Tunnel Field-Effect
Transistors International Conference on Solid State Devices and Materials,
Fukuoka, 2013, 2 pages. Y. Morita, T. Mori, S. Migita, W. Mizubayashi,
A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y. Liu, M. Masahara,
H. Ota
96. Experimental Study of 3D Fin-Channel Charge Trapping Type Flash Memories
with TiN Metal and Poly-Si Gates International Conference on Solid State
Devices and Materials, Fukuoka, 2013, 2 pages. Y. Liu, T. Matsukawa, K.
Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi,
Y. Morita, S. Migita, H. Ota, M. Masahara
97. Influence of work function variation in a metal gate on fluctuation
of current-onset voltage for undoped-channel FinFETs International Conference
on Solid State Devices and Materials, Fukuoka, 2013, 2 pages. T. Matsukawa,
Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. Ouchi, W. Mizubayashi,
H. Ota, S. Migita, Y. Morita, M. Msahara
98. Performance Limit of Parallel Electric Field Tunnel FET and Improvement
by Modified Gate and Channel Configurations 43rd European Solid State Device
Research Conference, Bucharest, 2013, 4 pages. Y. Morita, T. Mori, S. Migita,
W. Mizubayashi, A. Tanabe, K. Fukuda, K. Endo, T. Matsukawa, S. O’uchi,
Y. Liu, M. Masahara, H. Ota
99. Charge Trapping Type FinFET Flash Memory with Al2O3 Blocking Layer
IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified
Conference, Monterey, 2013, 2 pages. Y. Liu, T. Nabatame, T. Matsukawa,
K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi,
Y. Morita, S. Migita, H. Ota, T. Chikyo, M. Masahara 100. Heated Ion Implantation
Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs International
Electron Devices Meeting, Washington D.C., 2013, 4 pages. W. Mizubayashi,
H. Onoda, Y. Nakajima, Y. Ishikawa, T. Matsukawa, K. Endo, Y. Liu, S. O’uchi,
J. Tsukada, H. Yamauchi, S. Migita, Y. Morita, H. Ota, M. Masahara
101. Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing
2014 Symposium on VLSI Technology, Honolulu, 2014, 2 pages. T. Matsukawa,
K. Fukuda, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. Ouchi,
W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Msahara
102. Fabrication and Characterization of 3D Fin-Channel MANOS Type Flash
Memory Silicon Nanoelectronics Workshop, Honolulu, 2014, 2 pages. Y. Liu,
T. Nabatame, Y. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi,
Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyo, M.
Masahara
103. Comparative Study of Floating Gate Type 3D Fin-Channel Flash Memorires
with Different Channel Shapes and Interpoly Dielectric Layers International
Conference on Solid State Device and Materials, Tsukuba, 2014, 2 pages.
Y. Liu, T. Nabatame, N. Ngyuene, Y. Matsukawa, K. Endo, S. O’uchi, J. Tsukada,
H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota,
T. Chikyo, M. Masahara
104. Charge Trapping Type SOI-FinFET Flash Memory 225th Electrochemical
Society Meeting, Orlando, 2014, 19 pages. Y. Liu, T. Nabatame, N. Ngyuene,
Y. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa,
W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyo, M. Masahara
105. Variation behavior of tunnel-FETs originated from dopant concentration
at source region and channel edge configuration 44th European Solid-State
Device Research Conference, Venice, 2014, 4 pages. S. Migita, T. Matsukawa,
T. Mori, K. Fukuda, Y. Morita, W. Mizubayashi, K. Endo, Y. Liu, S. O'uchi,
M. Masahara, H. Ota
106. Improvement of Epitaxial Channel Quality on Heavily Arsenic- and Boron-doped
Si surfaces and Its Impact on Tunnel FET Performance 44th European Solid-State
Device Research Conference, Venice, 2014, 4 pages. Y. Morita, T. Mori,
S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo,
S. O’uchi, Y. Liu, M. Masahara, H. Ota
107. Experimental Study of Charge Trapping Type FinFET Flash MemoryIEEE
International Nanoelectronics Conference, Sapporo, 2014, 4 pages. Y. Liu,
T. Nabatame, N. Ngyuene, Y. Matsukawa, K. Endo, S. O’uchi, J. Tsukada,
H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota,
T. Chikyo, M. Masahara
108. Experimental Realization of Complementary p- and n- Tunnel FinFETs
with Subthreshold Slopes of less than 60 mV/decade and Very Low (pA/um)
Off-Current on a Si CMOS Platform International Electron Devices Meeting,
San Francisco, 2014, 4 pages. Y. Morita, T. Mori, S. Migita, W. Mizubayashi,
A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y. Liu, M. Masahara,
H. Ota
109. Scaling Breakthrough for Analog/Digital Circuits by Suppressing Variability
and Low-Frequency Noise for FinFETs by Amorphous Metal Gate Technology
International Electron Devices Meeting, San Francisco, 2014, 4 pages. T.
Matsukawa, K. Fukuda, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa,
S. Ouchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Msahara
110. Accurate Prediction of PBTI Lifetime for N-type Fin-Channel Tunnel
FETs International Electron Devices Meeting, San Francisco, 2014, 4 pages.
W. Mizubayashi, T. Mori, Y. Liu, T. Matsukawa, Y. Ishikawa, K. Endo, S.
O’uchi, J. Tsukada, H. Yamauchi, Y. Morita, S. Migita, H. Ota, M. Masahara
111. Experimetal Study of Variability in Polycrystalline and Crystalline
Silicon Channel FinFET CMOS Inverters International Symposium on VLSI Technology,
Systems and Applications, Hsinchu, 2015, 4 pages. Y. Liu, Y. Hori, M. Ohno,
T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa,
W. Mizubayashi, Y. Morita, S. Migita, H. Ota, M. Masahara
112. PBTI for N-type Tunnel FinFETs IEEE International Conference on Integrated
Circuit Design and Technology, Leuven, 2015, 4 pages. W. Mizubayashi, T.
Mori, K. Fukuda, Y. Liu, T. Matsukawa, Y. Ishikawa, K. Endo, S. O’uchi,
J. Tsukada, H. Yamauchi, Y. Morita, S. Migita, H. Ota, M. Masahara
113. Variability Suppression of FinFETs by Smoothing Sidewall Roughness
Using Ion Beam Etching Technology Silicon Nanoelectronics Workshop, Kyoto,
2015, 2 pages. T. Matsukawa, K. Endo, Y. Akasaka, S. Kamiya, M. Ikeda,
K. Tsunekawa, T. Nakagawa, Y. Liu, M. Masahara
114. 0.8-V Rail-to-Rail Operational Amplifier with Near-Vt Gain-Boosting
Stage in FinFET Technology for IoT Sensor Nodes IEEE SOI-3D-Subthreshold
Microelectronics Technology Unified Conference, Rohnert Park, 2015, 3 pages.
S. Ouchi, K. Endo, Y. Liu, T. Matsukawa, Y. Ishikawa, J. Tsukada, H. Yamauchi,
W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara
115. Introduction of SiGe/Si Heterojunction into Novel Multilayer Tunnel
FinFETs International Conference on Solid State Device and Materials, Sapporo,
2015, 2 pages. Y. Morita, T. Mori, K. Fukuda, W. Mizubayashi, S. Migita,
K. Endo, S. O’uchi, Y. Liu, M. Masahara, H. Ota
116. Novel Wafer-Scale Uniform Layer-by-Layer Etching Technology for Line
Edge Roughness Reduction and Surface Flattening of 3D Ge Channels International
Electron Devices Meeting, Washington D.C., 2015, 4 pages. Y. Morita, T.
Maeda, H. Ota, W. Mizubayashi, S. O’uchi, M. Masahara, T. Matsukawa, K.
Endo
117. Understanding of BTI for tunnel FETs International Electron Devices
Meeting, Washington D.C., 2015, 4 pages. W. Mizubayashi, T. Mori, K. Fukuda,
Y. Ishikawa, Y. Morita, S. Migita, H. Ota, Y. X. Liu, S. O'uchi, J. Tsukada,
H. Yamauchi, T. Matsukawa, M. Masahara, K. Endo
118. Low Temperature Microwave Annealed FinFETs with Less Vth Variability
International Symposium on VLSI Technology, Systems and Applications, Hsinchu,
2016, 2 pages. K. Endo, Y. Lee, Y. Ishikawa, F. -K. Hsueh, P. -J. Sung,
Y. Liu, T. Matsukawa, S. O’uchi, J. Tsukada, H. Yamauchi
119. Defect-Free Germanium Etching for 3D Fin MOSFET Using Neutral Beam
Etching IEEE International Conference on Nanotechnology, Sendai, 2016,
3 pages. En-Tzu Lee, Shuichi Noda, Wataru Mizubayashi, Kazuhiko Endo, Seiji
Samukawa 120. Lowering of effective work function induced by metal carbide/HfO2
interface dipole for advanced CMOS IEEE International Conference on Nanotechnology,
Sendai, 2016, 4 pages. W. Mizubayashi, H. Ota, S. Migita, Y. Morita, and
K. Endo
121. Spike-based Time-domain Weighted-sum Calculation Using Nanodevices
for Low Power Operation IEEE International Conference on Nanotechnology,
Sendai, 2016, 3 pages. T. Morie, H. Liang, T. Tohara, H. Tanaka, M. Igarashi,
S. Samukawa, K. Endo, and Y. Takahashi
122. Bias Temperature Instability in Tunnel FETs International Conference
on Solid State Device and Materials, Tsukuba, 2016, 2 pages. W. Mizubayashi,
T. Mori, K. Fukuda, Y. Ishikawa, Y. Morita, S. Migita, H. Ota, Y. X. Liu,
S. O'uchi, J. Tsukada, H. Yamauchi, T. Matsukawa, M. Masahara, K. Endo
123. On the Drain Bias Dependence of Tunnel FETs International Conference
on Solid State Device and Materials, Tsukuba, 2016, 2 pages. K. Fukuda,
T. Mori, H. Asai, J. Hattori, W. Mizubayashi, Y. Morita, H. Fuketa, S.
Migita, H. Ota, M. Masahara, K. Endo, T. Matsukawa
124. Tunnel FinFET CMOS Inverter with Very Low Short-Circuit Current for
Ultra-Low Power IoT Application International Conference on Solid State
Device and Materials, Tsukuba, 2016, 2 pages. Y. Morita, K. Fukuda, Y.
Liu, T. Mori, W. Mizubayashi, S. O'uchi, H. Fuketa, S. Otsuka, S. Migita,
M. Masahara, K. Endo, H. Ota, T. Matsukawa
125. Morphology and electrical studies on MoS2 field-effect transistor
irradiated with N2 plasma The 9th annual Recent Progress in Graphene and
Two-dimensional Materials Research Conference (RPGR2017), Singapore, 2017,
2 pages A. Ando, T. Irisawa, N. Okada, J. Miyawaki, T. Kubo, T. Mori and
K. Endo
126. Short Channel Modeling of Tunnel FET International Conference on Solid
State Device and Materials, Sendai, 2017, 2 pages. K. Fukuda, E. Asai,
S. Migita, H. Ota, K. Endo and T. Matsukawa
127. Enhancement of Capacitance Benefit by Drain Offset Structure in TFET
Circuit Speed Associated with Tunneling Probability Increase International
Conference on Solid State Device and Materials, Sendai, 2017, 2 pages E.
Asai, T. Mori, T. Matsukawa, J. Hattori, K. Endo and K. Fukuda
128. Cluster-Preforming-Deposited Amorphous WSin (n = 12) Insertion Film
of Low SBH and High Diffusion Barrier for Direct Cu Contact International
Electron Devices Meeting, San Francisco, 2017, 4 pages. N. Okada, N. Uchida,
S. Ogawa, K. Endo and T. Kanayama
129. Position Control and Gas Source CVD Growth Technologies of 2D MX2
Materials for Real LSI Applications IEEE Electron Devices Technology and
Manufacturing Conference, Kobe, 2018, 3 pages. T. Irisawa, N. Okada, W.
Mizubayashi, T. Mori, W. Chang, K. Koga, A. Ando, K. Endo, S. Sasaki, N.
Endo, Y. Miyata
130. Importance of Self-Consistent and Transient Technology Computer-Aided
Design Simulation of a Negative Capacitance Transistor International Conference
on Solid State Devices and Materials, Tokyo, 2018, 2 pages. H. Ota, T.
Ikegami, J. Hattori, H. Asai, K. Fukuda, K. Endo, S. Migita, A. Toriumi
1
31. Steep Switching Less Than 15 mV/decade in Silicon-on-Insulator Tunnel
FETs by Trimmed-Gate Structure International Conference on Solid State
Devices and Materials, Tokyo, 2018, 2 pages. H. Asai, T. Mori, T. Matsukawa,
J. Hattori, K. Endo, K. Fukuda
132. Multidomain Dynamics of Ferroelectric Polarization and its Coherency-Breaking
in Negative Capacitance Field-Effect Transistors International Electron
Devices Meeting, San Francisco, 2018, 4 pages. H. Ota, T. Ikegami, K Fukuda,
J. Hattori, H. Asai, K. Endo, S. Migita, A. Toriumi
133. Atomic Layer Etching, Deposition and Modification Processes for Novel
Nano-materials and Nano-devices 3rd Asia-Pacific Conference on Plasma Physics,
PL-26, Hefei, China, 2019, 1 page. Seiji Samukawa, Kazuhiko Endo
134. Analysis of charge-to-hot-carrier degradation in Ge pFinFETs 2020
IEEE International Reliability Physics Symposium (IRPS), Dallas, 2020,
4 pages. W. Mizubayashi, H. Oka, K. Fukuda, Y. Ishikawa, K. Endo
135. Toward Long-coherence-time Si Spin Qubit: The Origin of Low-frequency
Noise in Cryo-CMOS 2020 Symposium on VLSI Technology, Virtual meeting,
2020, 2 pages. H. Oka, T. Matsukawa, K. Kato, S. Iizuka, W. Mizubayashi,
K. Endo, T. Yasuda, T. Mori
136. Effects of Nb Oxide Films Controlled by Neutral Beam Oxidation on
Q-value of Superconducting Resonators 34th International Symposium on Superconductivity,
ED8-3, Virtual Meeting, 2021, 2 pages. Taichi Konno, Daisuke Ohori, Shuichi
Noda, Mutsuo Hidaka, Kazuhiko Endo, Hiroto Mukai, Akiyoshi Tomonaga, Jaw-Shen
Tsai, and Seiji Samukawa
137. Si Nanopillar/SiGe Composite Structure for Thermally Managed Nano-Devices
21st IEEE International Conference on Nanotechnology, ThAT2.5, Virtual
meeting, 2021, 4 pages. D. Ohori, M. Murata, A. Yamamoto, K. Endo, M.-H.
Chuang, M.-Y. Lee, Y. Li, J.-H. Tarng, Y.-J. Lee, and S. Samukawa
138. Surface Wettability of Nanopillar Array Structures Fabricated by Bio-Template
Ultimate Top-Down Processes 21st IEEE International Conference on Nanotechnology,
ThAT2.6, Virtual meeting, 2021, 4 pages. S. Takeuchi, D. Ohori, T. Ishida,
M. Tanaka, M. Sota, K. Endo, and S. Samukawa